1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor device and, more in particular, it relates to a method of manufacturing a semiconductor device of a structure in which a barrier metal layer is present between a semiconductor substrate such as a silicon substrate and a wiring layer formed thereon, as well as it relates to a method of manufacturing a semiconductor device using a silicide technique.
2. Description of the Prior Art
For improving the reliability of various kinds of elements in semiconductor devices, it has been conducted to form a barrier layer between a wiring layer and a semiconductor substrate, or preventing reaction between the wiring layer and an underlying semiconductor substrate (for example, Si substrate), for improvement of the close bondability of the wiring film, prevention of disconnection failure and prevention of stress migration. The barrier layer usually comprises metal (or alloy) or a metal compound, which is referred as a barrier metal layer. In the present invention, the term "barrier metal layer" is used for collectively indicating those having a barrier effect. As the material for forming the barrier metal layer, metals or metal compounds such as TiN, TiW, Ti or TiON, tungsten nitride, etc. are used (for the relevant technique in the prior art, refer to descriptions contained in IEDM 90 (1990 IEEE) pp 47-50, by E. O. Travis et. al, "A Scalable Submicron Contact Technology Using Conformal LPCVD TiN").
With the recent demand for the integration of semiconductor devices, the size of various kinds of devices has been made finer and along therewith, the size of contact holes, has also been made finer, for example, in ULSI. Therefore, if the barrier metal used for such a structure is formed by deposition in a contact hole 8 by an existent sputtering method as in the known literature described above as shown in FIG. 3, no sufficient coverage can be obtained. That is, since the coverage is deteriorated by the refinement of the contact hole 8, a film of a not-uniform barrier metal 70 is formed in the contact hole 8 disposed to the interlayer film 6 as shown in FIG. 3 to close the opening at the opening portion of the contact hole 8 thereby reducing the hole diameter R for burying a wiring material such as Al and reducing the thickness of the barrier metal layer 70 at the bottom of the contact hole 8. Accordingly, a cavity referred to as a void is liable to be formed as indicated by a broken line also in a wiring material (for example, Al) formed to the upper layer as shown in FIG. 3, which deteriorates the reliability in the connection and brings about a problem of punch through of the wiring material into the underlying Si. Therefore, junction leakage is increased to possibly reduce the reliability, for example, of a transistor as a semiconductor device.
As a countermeasure for the problem described above, a method of forming a taper to a contact hole for improving the coverage has been suggested. For instance, AsSG having a relatively low melting point is used as the material for the interlayer film 6, in which a contact hole 8 is formed and annealing is applied at about 900.degree. C. to conduct fellow for the hole 8 thereby forming a taper T1 as shown in FIG. 4(A). However, when this method adopted, there is a problem that the contact hole 8 is tapered reversely as shown in FIG. 4(B) (reversed taper is shown by T2). Therefore, no sufficient coverage can be obtained and, after all, this method neither provides drastic dissolution.
On the other hand, along with the progress in reducing the process rule of the device described above, it considered important to form an impurity diffusion region of a shallow junction with low resistivity in a semiconductor device for preventing an undesired effect such as short channel effect caused by the reduction of the size.
For reducing the resistivity, a salicide technique of selectively forming a silicide to the surface of a source-drain region (Self Aligned Silicide) has been known and an example of the salicide forming technique, is a known technique of applying Ar.sup.+ sputter etching to the surface of a substrate, then depositing a metal film and forming a silicide layer in self alignment by means of a two step RTA (Rapid Heat Treatment) (refer, for example, to "J. Electrochem. Soc." Vol. 137, No. 6, June, 1990, pp 1914-1917, published from The Electrochemical Society, Inc.
Further, a general method of forming a junction is ion implantation. In a usual process, an impurity is implanted into a silicon substrate for forming a source-drain region but crystal defects are liable to occur due to damages upon ion implantation. Junction leak due to crystal defects is not increased if the junction is deep but junction leak due to crystal defects is increased if the junction is shallow.
In view of the above, there has been a method of not conducting ion implantation directly to a substrate but previously forming a polysilicon layer or a silicide layer on a source-drain region, implanting an impurity into the polysilicon layer or the silicide layer by ion implantation and, subsequently, forming the impurity region by diffusion annealing and it is described, for example, in "Monthly Semiconductor World", May 1984, pp 49-53 (published by Press Journal Go.). The solid phase diffusion from the polysilicon layer or the silicide layer to the silicon substrate can suppress the occurrence of silicon crystal defects thereby suppressing the increase of the junction leak.
By the way, in a case of using a silicide for reducing the resistivity, it is necessary that it has a heat resistance of higher than 900.degree. C., because annealing at a high temperature above 900.degree. C. is necessary in order to diffuse the impurity from the silicide. Further, also in a case of not using the silicide, it is necessary to apply a high temperature annealing above 900.degree. C. in a process such as an activation annealing after contact ion implantation subsequent to the formation of a transistor.
However, a silicide such as TiSi.sub.2 alloyed by a usual heat treatment coagulates in a high temperature process about at 900.degree. C. to increase the sheet resistance. For instance, an experiment regarding the sheet resistance shows an example that the sheet resistance is increased from 10 ohm/.quadrature. to 300 ohm/.quadrature..